This application claims priority under 35 USC §119 to Korean Patent Application No. 2006-19485, filed on Feb. 28, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field Of The Invention
The present invention relates generally to integrated circuits, and more particularly, to an integrated circuit having multiple power domains with power lines that are connected together in a predetermined operating mode.
2. Background Of The Invention
A semiconductor integrated circuit fabricated as a conventional flash memory has generally used a power voltage of 5 Volts as an operating voltage. However, lower operating voltages are desired with higher integration and scaling-down of semiconductor integration circuits. For example, an operating voltage of about 1.0 V is used for a memory device, and an operating voltage of from about 0.6 Volts to about 1.3 Volts is used for a logic circuit such as a central processing unit (CPU) depending on an operating mode thereof.
When the operating voltage decreases, a noise margin of the semiconductor integrated circuit is reduced, and an allowable IR (current-resistance) voltage drop is reduced. Also, for higher integration, not only signal lines but also power lines of the integrated circuit become longer and thinner. Thus, the resistance of the power line increases that in turn significantly increases the IR voltage drop. Consequently, an operating frequency of the highly integrated circuit is lowered by the increased IR voltage drop.
In addition, more complicated integrated circuits are fabricated with more gates for high performance. Since power consumption increases with higher number of gates, technology for reducing power consumption is desired. To address such issues, multi-power domain technology is used for separating power domains among different functional blocks with control of turning on/off the power supplied to the multiple power domains depending on operating modes of the functional blocks.
FIG. 1 is a block diagram of a semiconductor integrated circuit 10 according to the conventional art. Referring to FIG. 1, the integrated circuit 10 includes a regulator 11 for generating internal operating voltages and two power domains 13 and 15. Each of the power domains 13 and 15 independently receives a respective voltage from the regulator 11.
That is, the power domain 13 receives a first operating voltage V from the regulator 11, and the power domain 11 receives a second operating voltage V′ from the regulator 11. The first and second operating voltages V and V′ may each be set to a same voltage level or to different voltage levels, as disclosed in U.S. Pat. No. 6,650,589.
However, power lines of the power domains 13 and 15 in the prior art remain separated (i.e., disconnected) from each-other. Thus in the prior art, the IR voltage drops in the separated power domains 13 and 15 may be higher and more difficult to control than when the integrated circuit has one power domain. For example, the IR voltage drop within one of the power domains 13 and 15 may become high enough for significantly degrading the operating frequency of the integrated circuit. Nevertheless, multiple power domains for an integrated circuit are desired for minimizing power consumption.